A prior art control apparatus will be described. In the following description, a variable frequency oscillator (hereinafter, referred to as "VFO") is used as a variable frequency generating means and a PLL circuit is used as a control apparatus.
The VFO which is an important constitutional element of a PLL circuit has variations dependent on elements, and further it is well known that it has variations dependent on the usage environment, such as a power supply voltage. FIG. 4 shows an example of control input vs. output frequency characteristics of the VFO. In the figure, reference character a represents a characteristic which is to be the design center, reference characters b and c represent characteristics in cases where the characteristics of the VFO varies. In order to enable a preferable operation as a PLL by using such three kinds of VFOs to obtain a predetermined frequency f.sub.O, input signals of v.sub.a, v.sub.b, and v.sub.c are required as control inputs of the three VFOs. As a method of automatically correcting the variations of the characteristics of the VFO, there is a technique disclosed in Japanese Laid-open Patent Publication No. Sho 62-97428.
FIG. 6 is a block diagram of a control apparatus which conducts such an automatic correction. In FIG. 6, reference numeral 1 denotes a VFO outputting a variable frequency signal D, the frequency of which varies in response to the control signal C. Reference numeral 2 denotes a phase comparator circuit for detecting the phase difference between the variable frequency signal D and the input signal A from the outside to output an error detection signal B. Reference numeral 3 denotes a correction circuit for detecting the deviation of the frequency of the variable frequency signal D from a predetermined value (f.sub.O) to output a correction signal E. Reference numeral 4 denotes an adder.
The device will operate as follows.
When the input signal A does not exist, the phase comparator 2 outputs 0 as the error signal B. Then, a control circuit which makes the frequency of the signal D of the VFO 1 be a predetermined value f.sub.O is constituted by the adder 4, the VFO 1, and the correction circuit 3, and the frequency of the signal D becomes f.sub.O. On the other hand, when the signal A is input, the signal D becomes equal to the predetermined frequency f.sub.O, and the signal D synchronized with the input signal A is obtained as the output of the PLL.
FIG. 5 shows characteristics of the signal D with respect to the signal C of FIG. 6. That is, the correction signals v.sub.a, v.sub.b, and v.sub.c shown in FIG. 4 are obtained from the correction circuit 3, and a predetermined frequency f.sub.O is obtained at a single value (for example, O) as the control signal C.
However, as is apparent from the curves a, b', and c' of FIG. 5, the control input vs. output frequency characteristics vary dependent on the variations of the characteristics of the VFO 1. That is, in the prior art control apparatus, the variation of the sensitivity of the VFO 1 is not corrected, thereby resulting in a large loss in the controllability.